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Tried to fix formatting issues in github pages in the README. #3

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stephenneuendorffer merged 1 commit intoXilinx:mainfrom
nishraptor:main
Sep 1, 2021
Merged

Tried to fix formatting issues in github pages in the README. #3
stephenneuendorffer merged 1 commit intoXilinx:mainfrom
nishraptor:main

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Fixed links to correct tests, and tried to fix the formatting issues in the github pages README for the routing section by adding an empty line.

@stephenneuendorffer stephenneuendorffer merged commit a5a67d4 into Xilinx:main Sep 1, 2021
fifield added a commit that referenced this pull request Dec 20, 2022
The moral of the story is to try the URL before committing it.
fifield added a commit that referenced this pull request Oct 23, 2025
… improve error decoding

- Fix path normalization logic in prepend_path() to always normalize paths
  even when there's no existing PATH (suggestion #3)
- Add XRT bin path prepending to programming_examples and programming_guide
  lit.cfg.py files to ensure more recent aiebu-asm is used (suggestion #2)
- Add error decoding robustness in detect_peano() using errors='ignore'
  parameter for consistency with detect_rocm() and detect_xrt() (suggestion #4)
andrej pushed a commit to andrej/mlir-aie that referenced this pull request Mar 20, 2026
Fixed 3 bugs in aiecc.cpp where output files were written to the
current working directory instead of the specified tmpdir:

1. Bug #1 (line 3533): --aie-generate-npu-insts checked generateNpuInsts
   flag instead of checking if the path is absolute. This caused NPU
   instruction .bin files to be written to CWD.

2. Bug #2 (line 3702): --aie-generate-ctrlpkt's else branch for the
   control packet binary just reassigned the filename instead of
   prepending tmpDirName.

3. Bug Xilinx#3 (line 3763): Same issue as Bug #2 for the DMA sequence binary.

These bugs caused race conditions and spurious test failures when
multiple tests ran in parallel (documented in FINDINGS.md). The fix
ensures all generated .bin files are written to the tmpdir unless
an absolute path is specified.

Co-Authored-By: Claude Opus 4.6 <[email protected]>
andrej pushed a commit to andrej/mlir-aie that referenced this pull request Mar 21, 2026
…ed (issue Xilinx#3), extracting init values correctly from maskwrite operations; 6 blocking issues remain including missing shim tiles, flows, and core operations.
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2 participants